Computer networks, such as data centers or High-Performance Computing (HPC) compute-node clusters, typically use network elements such as switches and routers that are interconnected using various interconnection topologies. Some known topologies include, for example, mesh, Fat-Tree (FT) and Dragonfly (DF).
The Dragonfly topology is described, for example, by Kim et al., in “Technology-Driven, Highly-Scalable Dragonfly Topology,” Proceedings of the 2008 International Symposium on Computer Architecture, Jun. 21-25, 2008, pages 77-88, which is incorporated herein by reference. U.S. Patent Application Publication 2010/0049942 to Kim et al., whose disclosure is incorporated herein by reference, describes a Dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.
Jiang et al. describe indirect global adaptive routing (IAR) schemes in Dragonfly networks, in which the adaptive routing decision uses information that is not directly available at the source router, in “Indirect Adaptive Routing on Large Scale Interconnection Networks,” Proceedings of the 2009 International Symposium on Computer Architecture, Jun. 20-24, 2009, pages 220-231, which is incorporated herein by reference.
Garcia et al. describe a routing/flow-control scheme for Dragonfly networks, which decouples the routing and the deadlock avoidance mechanisms, in “On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks,” Proceedings of the 2012 International Conference on Parallel Processing (ICPP), Sep. 10-13, 2012, which is incorporated herein by reference.
Prisacari et al. investigate indirect routing over Dragonfly networks, in in “Performance implications of remote-only load balancing under adversarial traffic in Dragonflies,” Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, Jan. 22, 2014, which is incorporated herein by reference.
Matsuoka describes techniques for implementing high-bandwidth collective communications, in “You Don't Really Need Big Fat Switches Anymore—Almost,” Information Processing Society of Japan (IPSJ) Journal, 2008, which is incorporated herein by reference.